1. Technical Field
The present invention relates generally to an improved data processing system and method. More specifically, the present invention is directed to an apparatus and method for using a single bank of electrical fuses (eFuses) to successively store testing data from multiple stages of testing.
2. Description of Related Art
Traditionally, the manufacturers of complex integrated circuits with arrays of components use multiple stages of testing to test the operation of the various components. For example, a manufacturer may first test the components of the integrated circuit at normal temperature and voltage in wafer form. The manufacturer may then run additional tests of the good components, i.e. those that pass the initial test, under stress. The manufacturer may then test the integrated circuit again when it is packaged. Other tests may also be included in the test regime to check the operation of the components of the integrated circuit under various conditions.
For example, large integrated circuits and processors typically include large arrays of memory cells as part of their design. To ensure a reasonable yield, these arrays have built-in spare cells, i.e. redundant cells, that may be substituted for any less than perfect cell. When these large arrays are tested, it is determined which cells need to be mapped to the spare or redundant cells of the array of memory cells. This information is transformed into data that is referred to as array redundancy data.
The data that is required for each cell substitution is called a repair and the correction performed based on this data is referred to as a repair action. These repair actions are necessary to skip over the non-functional cells in the array, and map to the redundant cells. These repair actions are loaded serially, one after the other. Once an array tester determines the required array redundancy data or the required repair actions, this data must be reloaded at power-on of the integrated circuit device or processor.
Each of the tests may produce array redundancy data which may be used to correct the arrays of components upon power-on. This array redundancy data, once verified, is typically stored in an area of the integrated circuit device or processor that can be programmed at test time, such as a bank of laser fuses, electrical fuses (eFuses) or other type of storage device. On a large integrated circuit device or processor, there is a large amount of array redundancy data that can take up large amounts of eFuses. Large numbers of eFuses occupy a large area of the device.
In addition, for each stage of testing, a specific dedicated separate bank of eFuses, located on the integrated circuit, is required to store the array redundancy data generated by that stage of testing. Each of these separate banks of eFuses thus, requires its own separate device area on the integrated circuit and its own control logic. Moreover, if there are any eFuses left over from one stage of testing, they cannot be used in any subsequent stage of testing.
Thus, the known mechanisms for storing and using array redundancy data from multiple stages of testing of an integrated circuit device result in excess area of the integrated circuit device or processor being dedicated to banks of eFuses and result in wasted space when eFuses are not able to be utilized from one stage of testing to the next. This is undesirable in that the extra area and logic impact the function and cost of the overall integrated circuit device or processor. Moreover, if the device is larger, then more power is needed to operate it.
In view of the above, it would be beneficial to have an apparatus and method for reducing the amount of area on an integrated circuit device that is needed for providing banks of eFuses. Moreover, it would be beneficial to have an apparatus and method that reduces the amount of wasted space generated by the inability to use eFuses from one test to the next in a series of multiple test stages.